A degree of integration in a semiconductor integrated circuit, particularly in an integrated circuit using a MOS transistor, has been increasing year by year. Along with the increase in the degree of integration, miniaturization of the MOS transistor used therein has progressed to a nano region. The progress in miniaturization of the MOS transistor gives rise to a problem, such as difficulty in suppressing a leak current, which poses an impediment to sufficiently reducing a circuit occupancy area while meeting a requirement of ensuring a necessary amount of current. With a view to solving this problem, there has been proposed a surrounding gate transistor (SGT) having a structure in which a source, a gate and a drain are arranged in a direction perpendicular to a substrate, wherein the gate is formed to surround a pillar-shaped semiconductor layer (see, for example, the following Patent Documents 1 to 3).
In the SGT, a channel region is provided around a side surface of the pillar-shaped semiconductor, so that a large gate width is achieved within a small occupancy area. This means that it is necessary to allow a large ON-current to flow through the small occupancy area. However, if the source, drain and gate have a high resistance, it becomes difficult to apply a desired voltage for allowing the flow of a large ON-current, to the source, drain and gate. Therefore, it is required to provide an SGT production method including a design technique for reducing the resistance of the source, drain and gate. As another condition for allowing the flow of a large ON-current, it is also required to reduce a resistance of a contact.
In a conventional MOS transistor, a gate is formed by depositing a gate material, transferring a gate pattern to a resist on a substrate by lithography, and etching the gate material. In other words, in the conventional MOS transistor, a gate length is designed based on a gate pattern.
In the SGT, a current flows in a direction perpendicular to the substrate, because the side surface of the pillar-shaped semiconductor serves as a channel region. Thus, in the SGT, a gate length is not designed based on a gate pattern but based on a production method, so that the gate length and a variation therein are determined by a production method.
In the SGT, as measures for suppressing an increase in leak current occurring along with miniaturization, it is required to reduce a diameter of the pillar-shaped semiconductor. It is also required to provide a production method capable of optimizing the source and drain to suppress short-channel effects so as to reduce a leak current.
As with the conventional MOS transistor, the SGT also has a need for reducing a production cost. For this purpose, it is required to reduce the number of production steps.
Instead of polysilicon, a metal can be used as a material for a gate electrode to suppress depletion and reduce a resistance of the gate electrode. In this case, any production step subsequent to the step of forming a metal gate has to be designed while taking into account metal contamination due to the metal gate.
Patent Document 1: JP 2-71556A
Patent Document 2: JP 2-188966A
Patent Document 3: JP 3-145761A